The present invention concerns a semiconductor component with a Schottky junction, intended for fast logic circuits and microwave amplification.
Numerous component structures have already been proposed for this purpose, among which we may cite bipolar homojunction transistors, bipolar heterojunction transistors, MESFET transistors (MEtal-Silicon Field-Effect Transistor), transistors of the type known as TEGFET (Two-dimension Electron Gas Field-Effect Transistor) or HEMT (High Electron Mobility Transistor), and so-called permeable-base transistors (whose structure will be specified later in the present description).
Generally speaking, at microwave frequencies, maximum amplification is desired, at the highest possible frequency and with the highest possible output power. These three factors (gain, frequency and power), however, are not independent of each other, which means that compromise and optimization are necessary.
To a first approximation, it can be said that the aptitude to amplify is limited in frequency by the series resistance R and the parallel capacitance C at the input (giving a time constant RC limiting the maximum input frequency) and by the transit time of charge carriers within the component, this transit time also being directly related to the power available at output.
With fast logic circuits, it can be said, again as a first approximation, that devices are needed with a high slope and low input and output capacitance to be able to work at high clock speeds.
The MESFET transistor, with its usual structure (i.e. a horizontal structure, where the three source, grid and drain electrodes are in the same plane), has a fairly favorable product RC inherent in this structure. However, owing to this structure, the transit time is relatively long. Moreover, the fact that the three electrodes are in the same plane does not facilitate the parallel installation of elementary transistors from the technological point of view--this is however necessary for powerful components.
In addition, if the input and output capacitances are relatively low, the mutual conductance is relatively high, which has a negative effect on the input product RC, and therefore on the maximum working frequency.
Finally, the MESFET is generally made on gallium arsenide, which considerably increases the complexity of manufacture as well as the cost.
To remedy these disadvantages, the structure known as the "permeable-base transistor" was proposed, illustrated in diagrammatic form in FIG. 1.
This structure is a vertical structure with stacked electrodes comprising, on a substrate 1, a strongly doped layer 2 (for example N.sup.+), then a weakly doped layer 3 (for example N), then another strongly doped layer 4 (for example N.sup.+). Within the layer 3 are buried, approximately at mid-height, a series of metallic electrodes 5 (for example in the form of a series of fingers) which are interconnected and linked to the same potential.
The different layers 2, 3, 4 are formed by epitaxy, typically on gallium arsenide. The material of which the buried electrode 5 is made is chosen so as to be compatible with this epitaxy (for example, tungsten is chosen for epitaxy on gallium arsenide).
Layer 2 constitutes an electrode known as the emitter electrode and layer 4 an electrode known as the collector electrode (or the reverse; throughout the present description, the two structures will be considered as equivalent); the electrode 5 constitutes an electrode known as the base electrode, defining a semiconducting channel 6 between the collector 4 and the emitter 2, whose conduction can be controlled by the polarization of this base 5, so that electrons can be selectively permitted to circulate or prevented from circulating between the collector and the emitter through the metal fingers of the base 5 (hence the term "permeable-base").
The general operation of such a permeable-base transistor is explained in FIG. 2.
Essentially, the polarization of the electrode 5 creates space charge zones, delimited by the dashed curve in FIG. 2, and whose overlapping at the semiconducting channel 6 creates a potential barrier to be crossed by the electrons wishing to circulate in this channel between the collector and the emitter. The component is thus controlled like a bipolar transistor, and this is why the electrodes 2, 5 and 4 are respectively called "emitter", "base" and "collector".
It will be noted that, if the distance d between the fingers of the electrode 5 was increased, the space charge zones would progressively become simply adjacent (medium d, FIG. 3), with therefore a null potential barrier for the electron, and then distant (large d, FIG. 4), thus opening the conducting channel 6.
In the first case (FIG. 3), the situation would be that of a vertical MESFET normally blocked, the electrodes 2, 5 and 4 corresponding respectively to the source, the grid and the drain. It is possible to make this MESFET conducting by polarizing the electrode 5.
In the second case (FIG. 4), the situation would be that of a normally conducting MESFET, which can be blocked by polarizing the electrode 5.
It can be seen that in both these cases, the control of the component would no longer be analogous to that of a bipolar transistor as in the case illustrated in FIG. 2, but would be that of a field-effect transistor.
It will nevertheless be noticed that, physically, the structure remains the same in all three cases, although the electronic behavior and therefore the mode of operation (permeable-base transistor or field-effect) is modified as a function of the distance d--large or small--between the electrodes 5.
As will be seen later, the present invention will cover all the possible modes of operation of such a structure; for this reason, to avoid any restrictive terminology, we shall in the rest of the present description call the electrode 5 (which is a base or a grid, depending on circumstances) the "control electrode", the electrode 2 (emitter or source) the "lower electrode" and the electrode 4 (collector or drain) the "upper electrode".
It should also be noted that it would be perfectly possible to invert the roles of the electrodes 2 and 4, the electrode 2 then being the collector (or drain) and the electrode 4 the emitter (or source). The invention will consider both these possibilities equally, and the terminology "lower electrode" and "upper electrode" has been chosen in particular because it does not imply a preconception of the respective electrical roles of these two electrodes 2 and 4.
Another known transistor structure, electrically equivalent to that in FIG. 1, has been represented in FIG. 5.
In this structure, the base electrode 5 is no longer a
buried electrode, but an electrode deposited at the bottom of a groove 7, the different grooves 7 delimiting fingers 8 in the semiconducting material, defining between the base electrodes 5 channels whose conduction will be controlled by the polarization of these base electrodes.
A first advantage of this structure is to be able to use for the base 5 a material independent of the epitaxy, and in addition to be able to increase the thickness of this base for example by adding metal, thus enabling its resistance, and therefore the input resistance of the component, to be reduced.
On the other hand, unlike the structure in FIG. 1, this structure is generally made not on GaAs but on silicon. It is an extremely delicate task to make grooves in GaAs, while this can be done without difficulty in silicon (technique commonly used for manufacturing DRAM memories). Moreover, it is difficult to control the surface state of the sides of grooves in GaAs, whose surface irregularities provoke the development of parasitic space charge zones. The surface state of silicon, on the other hand, is easily controlled, for example by appropriate passivation of the sides of the groove.
The manufacturing process of such a component on silicon is diagrammatically illustrated in FIGS. 6 to 9.
According to this process, after having formed the different layers 2, 3 and 4 by epitaxy with the appropriate dopings (FIG. 6), the grooves 7 are etched (FIG. 7) to leave semiconducting fingers 8 and the whole is covered with a passivation layer 9, for example of silicon dioxide or silicon nitride.
This passivation layer 9 is then directionally etched, so as to lay bare the bottoms 10 of the grooves 7 and the tops 11 of the semiconducting fingers, leaving however the passivation layer on the sides of the grooves.
A metallic deposit 12 is then formed at the bottom of the grooves (FIG. 8) enabling a Schottky junction to be constituted by the formation of a silicide of the metal.
An enrichment layer 13 of the metallic deposit 12 which will constitute the base of the component is then deposited (FIG. 9), so as to increase the thickness of the base and reduce the corresponding electrode resistance (and therefore the component's input RC). A metallization 14 is also deposited at the top of the semiconducting fingers 8, enabling connection to the layer 4 constituting the collector electrode.
This structure, although relatively easy to make on silicon, presents a number of disadvantages.
First, it will be noticed that the structure is composed essentially of a juxtaposition of useful regions (referenced I in FIG. 9), i.e. regions where the electrons circulate (channel 6, defined in the region of the semiconducting fingers 8, whose conduction is controlled by the polarization of the base electrodes 12) and parasitic regions, referenced II in FIG. 9, which are the regions situated directly under the base electrodes 12; these regions are of no use from the electronic point of view, since the controlled conduction occurs between the electrodes 12 and not below them.
These zones II are in fact doubly parasitic.
First, the zone referenced 15, i.e. the zone under the base 12, between the latter and the emitter 2, introduces a parasitic capacitance which deteriorates the input product RC and thus correspondingly limits the maximum working frequency of the component.
Secondly, the zone referenced 16, i.e. the zone between the side of the groove and the metallic enrichment deposit 13, can introduce a parasitic control applied to the component, the successive layers of metallization 13, passivation 9 and semiconductor of the region 8 then behaving as a structure of type MIS (Metal-Insulator-Silicon) or MOS (if the passivation insulator is an oxide) likely to trigger the component at the wrong moment.
This zone 16, in addition to the possibility of parasitic control, introduces a base/collector capacitance between the metallization 13 and the upper semiconducting layer 4. This capacitance, although reduced compared with the buried-base structure (shown in FIG. 1), remains relatively large.